FRAMINGHAM 27 OCTOBER 2010 - A number of chip manufacturers and European research institutions have banded together to figure out how redesign microprocessors so that they consume less energy when in use and leak less energy when in stand-by mode.
Called Steeper, the research project aims to eliminate processor power consumption almost entirely when chips are in stand-by mode, as well as cut power usage by 10 times when in use.
The Swiss University Ecole Polytechnique Federale de Lausanne (EPFL) is coordinating the project, and IBM's Zurich research lab, Infineon Technologies and Global Foundries are contributing expertise, as are six European research institutions. (Global Foundries' participation is still pending, according to the announcement.) The European Union's European Commission Seventh Framework Program is providing the funding.
"Our vision is to share this research to enable manufacturers to build the Holy Grail in electronics, a computer that utilizes negligible energy when it's in sleep mode, which we call the zero-watt PC," said EPFL project coordinator Adrian Lonescu. The design could also be applied to portable electronic device processors as well, where it could potentially extend battery life.
The three-year project will explore an alternative design to the standard CMOS (complementary metal-oxide-semiconductor) designs used to build virtually all commercially available computer chips today. The new approach will use nanowire-based TFETs (tunnel field effect transistors), as an alternative to the MOSFTs (metal--oxide--semiconductor field-effect transistors) used in CMOS chips.
Well-designed TFETs could cut the overall power requirement for chips, and virtually eliminate power usage when in standby mode, the researchers argue.
Unnecessary power consumption when in standby mode is of particular concern to the E.U. Even when processors are in stand-by mode they can still consume small amounts of paper, in much the same a leaky faucet may drip small amounts of water even when firmly closed. The E.U. has estimated that devices in standby mode already account for about 10% of all energy use within homes and offices.
The researchers hope the new design will allow for closing the transistor gate more tightly -- thereby cutting power leakage -- as well as require less voltage to open and close the gate. Specifically, the researchers want to reduce the chip operating voltage to 0.5 volt, or about an order-of-magnitude lower than today's processors.
The TFETs will be built from silicon and silicon-germanium materials, and will exploit quantum mechanical band-to-band tunneling to achieve more efficient switching capabilities. The semiconducting nanowires, only a few nanometers in diameter will control the transistor channels.
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