Subscribe / Unsubscribe Enewsletters | Login | Register

Pencil Banner

Chip makers fight dwindling gains in efficiency

James Niccolai | Feb. 24, 2011
The latest generation of graphics chips have 3 billion transistors and consume about 200 watts of energy. The numbers are impressive -- until you consider that the human brain has the equivalent of a trillion transistors and consumes just 20 watts of energy, or far less than it takes to run a light bulb.

The latest generation of graphics chips have 3 billion transistors and consume about 200 watts of energy. The numbers are impressive -- until you consider that the human brain has the equivalent of a trillion transistors and consumes just 20 watts of energy, or far less than it takes to run a light bulb.

Semiconductor makers are looking at the brain with envy these days as they deal with the latest challenge to their industry -- dwindling gains in power efficiency. It's long been a concern for chip designers, but it's taking on new urgency as the common techniques of scaling down power usage are losing their effectiveness.

"The set of factors that have worked for us for about the last decade seems to be scattering around the edges," said Jan Rabaey, a professor at the University of California, Berkeley's College of Engineering, who moderated a panel on the topic at the Solid-State Circuits Conference in San Francisco this week.

It's not an abstract concern, either. Steady improvements in power efficiency have been a key enabler of today's powerful computers, especially mobile devices like the iPhone, where battery life is crucial.

The biggest gains have come from "process shrinks," or the move to new manufacturing techniques that allow for smaller and smaller transistors. It's the regular advance that's best known for enabling Moore's Law, but it has also allowed the performance per watt of semiconductors to improve with each process generation.

Process shrinks historically gave a 3x boost in energy efficiency, but today's advances give only a 1.4x improvement, said Dan Dobberpuhl, a former chip engineer at Digital Equipment Corp., Broadcom and Apple.

"Below 30 nanometers we have to introduce new materials and new structures" to keep scaling transistor voltage down, Oh-Hyun Kwon, president Samsung Electronics, said earlier in the day.

Engineers have been employing other tricks to reduce power consumption, such as controlling leakage, but the returns there are getting smaller too. The panelists were asked for proposals to bring about "the next 10x reduction" in power usage.

New transistor designs are part of the answer, said Jack Sun, CTO at contract manufacturing giant TSMC. Options include a design called FinFET, which uses multiple gates on each transistor, and another design called the junctionless transistor.

Researchers have made "great progress" with FinFET, and TSMC hopes it can be used for the next generation of CMOS -- the industry's standard silicon manufacturing process, Sun said.

 

1  2  Next Page 

Sign up for Computerworld eNewsletters.